{
  "demo": {
    "form": "host build of the identical generated C plus an emulated run; never a mock-up presented as a device",
    "highest_tier": "emulated",
    "not_a_physical_demonstration": "This is a terminal transcript, not a demonstration. Every step ran on a development host or under an emulator over a fixture model; no ARM device executed any of it, and nothing here was timed. What an investor can watch work is a compiler refusing what it cannot prove and producing C a person can read, which is a real thing to watch and is not a product running on hardware.",
    "physical_demonstration_is": "the STM32F411 side-by-side: the same board running the compiled graph and the vendor control in turn, latency read live over the transcript; the recorded transcript is beside this registry",
    "run_it_yourself": "make PY=.venv-v1/bin/python v1.2-demo",
    "steps": [
      {
        "tier": "static",
        "title": "what this is"
      },
      {
        "tier": "host",
        "title": "the refusal path"
      },
      {
        "tier": "host",
        "title": "the fit report"
      },
      {
        "tier": "compiled_c",
        "title": "the model became C"
      },
      {
        "tier": "compiled_c",
        "title": "the identical C, built and run on this host against the oracle"
      },
      {
        "tier": "emulated",
        "title": "the real Cortex-M4 encodings under the pinned QEMU"
      },
      {
        "tier": "static",
        "title": "what you did not see"
      }
    ]
  },
  "kernels": {
    "admitted": 27,
    "disassembly_proved": 27,
    "emulated": 27,
    "host_exact": 27,
    "run_on_silicon": 9
  },
  "ladder": [
    {
      "cannot_establish": "that the real instructions have those semantics; anything about time",
      "establishes": "the family's arithmetic, given the model's semantics of the primitives",
      "id": "host",
      "tier": "compiled_c"
    },
    {
      "cannot_establish": "what the instructions compute; anything about time",
      "establishes": "that the delivered bytes contain the intended instructions and no scalar fallback, no floating point, no allocation, no host I/O",
      "id": "disassembly",
      "tier": "compile_only"
    },
    {
      "cannot_establish": "that the silicon agrees with the emulator; anything about time, memory timing, caches or wait states",
      "establishes": "that the real encodings, executed, reproduce the host result; that the emulator's model of each assertion matches the manual",
      "id": "emulated",
      "tier": "emulated"
    },
    {
      "cannot_establish": "nothing further; this is the top of the ladder",
      "establishes": "everything the rungs below establish, on the silicon, plus every timing and resource figure",
      "id": "board",
      "tier": "physical_hil"
    }
  ],
  "parity_assumption": "Tested, and held. Host-to-board parity has held without exception on every measured ESP32-S3 cell, and on the STM32F411 the full Armv7E-M corpus, the instruction-set probe and every campaign cell's oracle check agreed with the host byte for byte. The working assumption declared before silicon is now a measured fact on both boards.",
  "porting_cost": {
    "counts_cover": "Line counts are read from the tree at recording time; the files are uncommitted at that moment and the counts are exact for the bytes sealed with them.",
    "files_added": 8,
    "lines_hand_written": 829,
    "lines_in_the_isa_header": 413,
    "operation_family_lines_changed": 0
  },
  "rule": "Every figure names its evidence tier. The ESP32-S3 and the STM32F411 are measured on their boards; the other Cortex-M targets here are engineering targets at the emulated rung.",
  "schema": "microquant-v12-part1-public-v1",
  "status": "part-three-measured",
  "stm32f411_fit": {
    "complete_firmware_flash_bytes": 61912,
    "flash_bytes_free": 462376,
    "graft_delta_flash_bytes": 60616,
    "graft_delta_sram_bytes": 24880,
    "latency": "measured; see stm32f411_measured",
    "part": {
      "flash_bytes": 524288,
      "sram_bytes": 131072
    },
    "peak_internal_sram_bytes": 33084,
    "product_flash_bytes": 59340,
    "sram_bytes_free": 97988,
    "tier": "compile_only",
    "workspace_bytes": 24192
  },
  "stm32f411_measured": {
    "board": "WeAct MiniSTM32F4x1 carrying an STM32F411CEU6, 96 MHz core from the device",
    "cells_measured": 23,
    "cells_that_do_not_fit": 7,
    "clock_hz": 96000000,
    "dense_keyword": {
      "cmsis_nn_ms": 30.9,
      "faster_than_cmsis_nn": 2.22,
      "flash_smaller_than_cmsis_nn": 1.5,
      "microquant_ms": 13.9,
      "output_parity": 1.0,
      "product_flash_bytes": 268310,
      "sram_smaller_than_cmsis_nn": 9.7,
      "top1_cmsis_nn": 0.8012269938650307,
      "top1_recompressed_from_int8": 0.805521472392638,
      "top1_same_int4_file": 0.8010224948875255,
      "w8_disposition": "does-not-fit",
      "w8_fits_the_part": false
    },
    "keyword_spotting": {
      "cmsis_nn_ms": 99.8,
      "faster_than_cmsis_nn": 1.47,
      "faster_than_tflm_reference": 47.2,
      "flash_smaller_than_cmsis_nn": 3.4,
      "microquant_ms": 67.8,
      "output_parity": 1.0,
      "product_flash_bytes": 59080,
      "sram_smaller_than_cmsis_nn": 1.8,
      "st_edge_ai_flash_is_smaller": true,
      "st_edge_ai_flash_ratio": 1.1,
      "st_edge_ai_is_faster": false,
      "st_edge_ai_latency_ratio": 1.19,
      "st_edge_ai_ms": 80.4,
      "st_edge_ai_product_flash_bytes": 55358,
      "tflm_reference_ms": 3202.9
    },
    "reading": "MicroQuant is 47.2x faster than the vendor runtime's own kernels and 1.47x faster than CMSIS-NN. Both comparisons go MicroQuant's way on this target; the first measurement on this board did not, and the kernel work that reversed it is recorded operation by operation. The footprint is 3.3x less flash and 1.9x less static SRAM than the CMSIS-NN control. ST Edge AI, the chip maker's own compiler, is 1.19x slower than MicroQuant on this graph, in 0.97x the whole-image flash and 0.86x the static SRAM.",
    "tier": "physical_hil",
    "wake_vision": {
      "cmsis_nn_ms": 322.7,
      "faster_than_cmsis_nn": 2.41,
      "flash_smaller_than_cmsis_nn": 6.1,
      "microquant_ms": 133.9,
      "output_parity": 1.0,
      "st_edge_ai_flash_is_smaller": false,
      "st_edge_ai_flash_ratio": 1.0,
      "st_edge_ai_is_faster": false,
      "st_edge_ai_latency_ratio": 1.03,
      "st_edge_ai_ms": 137.8,
      "st_edge_ai_product_flash_bytes": 78803
    }
  },
  "targets": [
    {
      "on_support_contract": true,
      "state": "measured on the board; the sealed campaign",
      "target_id": "esp32s3-devkitc-1-n16r8-esp-idf-6.0.2",
      "tier": "physical_hil"
    },
    {
      "on_support_contract": true,
      "state": "measured on the board: the corpus, the instruction-set probe and the campaign all on the part",
      "target_id": "stm32f411-weact-ministm32f4x1-arm-gnu-15.2",
      "tier": "physical_hil"
    },
    {
      "on_support_contract": false,
      "state": "reference binding for the second ISA; no board planned",
      "target_id": "cortex-m55-mve-reference-arm-gnu-15.2",
      "tier": "compile_only"
    },
    {
      "on_support_contract": false,
      "state": "the third target: an Armv8-M Mainline core served by the Armv7E-M DSP binding with no new kernel source; no board planned",
      "target_id": "cortex-m33-an505-arm-gnu-15.2",
      "tier": "compile_only"
    },
    {
      "on_support_contract": false,
      "state": "the unaccelerated floor; every operation portable",
      "target_id": "cortex-m-skeleton-armv6m-arm-gnu-15.2",
      "tier": "compile_only"
    }
  ],
  "third_target_cost": {
    "files_added": 11,
    "files_added_hand_written": 6,
    "guide_gaps_found_and_fixed": 9,
    "lines_changed_in_any_operation_family": 0,
    "lines_hand_written": 278,
    "lines_of_new_isa_header": 0
  }
}